The Silicon Brief - 17 August 2026

Today's edition covers five developments chip professionals need before their first meeting: China's two leading foundries post record utilisation and signal further price increases, Samsung considers converting a Giheung R&D line into a 2 nm HBM production facility, TSMC confirms it has doubled CoWoS advanced packaging capacity every year for three consecutive years yet still cannot satisfy demand, Samsung formally locks High-NA EUV out of its 2 nm and 1.4 nm nodes, and a structural analysis from Semiconductor Engineering argues that the industry's competitive battleground has moved from the transistor to the system.

SMIC and Hua Hong post Q2 utilisation rates of 93.7% and 102.8%, respectively, and are raising wafer prices into the third quarter. SMIC shipped 2.869 million 8-inch-equivalent wafers in Q2 2026, up 14.4% quarter-on-quarter, while capacity utilisation rose to 93.7%; Hua Hong Grace Semiconductor ran at 102.8%, above nameplate capacity. Both companies guided gross margins higher - SMIC targets 26%-28% in Q3 - as AI-peripheral chip demand, including logic ICs, BCD power-management devices, and optical transceiver components, remains in short supply. For chip professionals, the data confirm that China's mature-node foundry cycle has entered a new upswing, with pricing power now firmly on the supply side.

Samsung is considering repurposing its Giheung NRD-K Line 2, currently under construction as an R&D facility, into a 2 nm foundry production line targeting HBM5 base dies for Nvidia. Samsung's NRD-K Line 2 would primarily target mass production of 2 nm logic base dies for next-generation HBM, with HBM5 expected to require over 50% higher operating speeds than HBM4E and to use Samsung's GAA-based 2 nm process. Equipment purchase orders have not yet been placed, leaving the plan subject to change, but the reported direction signals that Samsung intends to use its own foundry capacity - rather than outsourcing - to secure the logic dies that underpin its HBM roadmap through the end of the decade.

TSMC confirmed at the 2026 OCP APAC Summit in Taipei that it has doubled CoWoS advanced packaging capacity every year for the past three years and still cannot fully satisfy customer demand. TSMC's monthly CoWoS capacity is projected to reach 120,000-140,000 wafers by the end of 2026, up from approximately 35,000 wafers per month in late 2024, with Nvidia reported to have secured over 60% of the 2026 allocation. The company is simultaneously advancing CoPoS (Chip-on-Panel-on-Substrate), a panel-level successor technology, with pilot production targeted for mid-2027. The disclosure underscores that advanced packaging - not transistor scaling - is now the primary supply constraint for AI accelerator delivery.^[2]

Samsung Electronics formally confirmed on 11 August 2026 that it will not deploy High-NA EUV lithography until its 1 nm (A10) node, expected around 2030, keeping its 2 nm (SF2) and 1.4 nm (SF1.4) processes on existing 0.33 NA EUV equipment. Samsung's Park Chang-min disclosed the lithography strategy at the 2026 Next Generation Lithography and Patterning Conference, confirming that High-NA EUV will enter commercial production at the A10 node, roughly four years from now. The decision aligns Samsung with TSMC, which has also declined to use ASML's EXE:5200 High-NA scanner for its own 1.4 nm node, concentrating near-term High-NA volume at Intel's fabs. For equipment planners, it narrows the addressable market for High-NA tools in the 2026-2028 window considerably.

Semiconductor Engineering's "From Silicon to Systems" analysis argues that competitive advantage in the chip industry has structurally shifted from transistor density to integration strategy, ecosystem depth, and system-level differentiation. The piece observes that AI accelerators are no longer constrained primarily by transistor scaling but by integration strategy and package-level interconnect density, with compute die, HBM stacks, and I/O die assembled on silicon interposers now defining performance ceilings.^[1][2] For engineers and strategists, the implication is that companies controlling the full stack - process, packaging, memory, and software - hold a compounding advantage that pure-play transistor leadership alone cannot replicate.^[1]