Design & EDAFlowAccel's Joel Jorgensen argues chip teams must design their workflows before AI can help them hit tape-out
Joel Jorgensen of FlowAccel argues that AI tools alone won't save a tape-out schedule - teams must first design the cross-team workflows that let those tools compound into real gains.
15 Oct 2026
SemiconductorsETH Zürich and NYU find JEDEC test loops underestimate HBM2 power by up to 35.4%
Researchers at ETH Zürich and NYU tested 36 real HBM2 chips and found JEDEC-specified current loops can underestimate peak power by up to 35.4%, with implications for AI accelerator thermal design.
15 Oct 2026
SemiconductorsSandia and Luxembourg researchers map the exact leakage route in gate-all-around transistors
Researchers at Sandia and Luxembourg's LIST used quantum-transport simulations to spatially resolve gate-drain tunneling in GAAFETs, pinpointing where leakage current flows at the device level.
15 Oct 2026
SemiconductorsFortastra raises $30 million in Series A to build autonomous orbital security spacecraft
Torrance-based startup Fortastra has closed a $30 million Series A to develop maneuverable, autonomous spacecraft for on-orbit satellite protection, days after its first pair reached orbit.
15 Oct 2026
Design & EDAEric Hong outlines Mixel's mixed-signal IP strategy after Silvaco acquisition
Mixel VP of Engineering Eric Hong discusses the company's PHY and SerDes roadmap, its TSMC N2P debut, and how the Silvaco acquisition is reshaping its IP strategy.
14 Oct 2026
Design & EDAVSORA chair Sandra Rivera tells Bloomberg that AI inference demand is durable but consolidation is coming
VSORA chair Sandra Rivera appeared on Bloomberg's The Close on 24 July 2026, arguing that AI inference demand is real and durable - but that not every chip startup will survive the shakeout.
14 Oct 2026
SemiconductorsApplied Materials opens its $5 billion EPIC Center in Sunnyvale on 12 October
Applied Materials unveiled its $5 billion EPIC Center in Sunnyvale on 12 October 2026 - the world's largest facility for collaborative semiconductor equipment R&D, with TSMC, Intel, Samsung, Micron and SK hynix as founding partners.
14 Oct 2026
SemiconductorsHARTING's Han HC DCT contacts carry up to 20% more current through a dual-path design
HARTING's new Han HC DoubleContact Technology contacts route current through two parallel paths, delivering up to 20% higher capacity with improved safety and easier installation.
14 Oct 2026
SemiconductorsUniversity researchers propose on-chip monitors to catch bit-flip attacks in AI accelerators at runtime
Researchers from UF, UT Dallas, and RPI published BARE-AI on 6 October 2026 - a runtime framework that detects and repairs bit-flip attacks in AI accelerators with under 4% area overhead at 28 nm.
14 Oct 2026
Design & EDAOnto Innovation extends FAaST platform to map residual surface charge across wafers and panels in advanced packaging
Onto Innovation published details on 8 October 2026 of how its FAaST non-contact electrical metrology platform addresses residual charge buildup in advanced packaging flows.
13 Oct 2026
Design & EDACPO test equipment is chasing a device target that keeps moving
Test vendors are building CPO production tooling while connector standards, laser sources, and optical-engine designs are still in flux - a structural mismatch the industry has not yet resolved.
13 Oct 2026
SemiconductorsGalileo wins permits for two 125 MW battery storage projects in Italy, totalling 1.5 GWh
Zurich-based developer Galileo has secured planning consent for 250 MW / 1.5 GWh of battery storage in Italy, with a further ~100 MW expected in the coming weeks.
13 Oct 2026