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Every story we have published, newest first, across all three beats.

Generated imageDesign & EDA

Signaloid founder Phillip Stanley-Marbell steps down from Cambridge chair to run probabilistic computing startup full-time

SemiWiki's CEO interview with Phillip Stanley-Marbell traces his path from Bell Labs and Apple to founding Signaloid, a Cambridge spinout whose C0-ASIC targets 1000× performance-per-watt gains.

22 Aug 2026
Design & EDA
Design & EDA

TSMC's COUPE co-packaged optics platform enters production in the second half of 2026

TSMC's Compact Universal Photonic Engine moves from qualification to volume production in H2 2026, promising 2x power efficiency and 10x lower latency over pluggable optics.

22 Aug 2026
Generated imageSemiconductors

Semiconductor Engineering frames energy efficiency as the defining constraint for AI computing through 2030

Data center electricity is set to nearly double to 945 TWh by 2030, making energy efficiency the central strategic challenge - and opportunity - for every company deploying AI at scale.

22 Aug 2026
Generated imageSemiconductors

IBM joins two cryogenic modules in a step toward a 1,000-qubit system by 2027

IBM connected and cooled two modular cryogenic systems on 19 August 2026, reaching below 15 millikelvin - a hardware milestone on its path to the Quantum Starling system in 2029.

22 Aug 2026
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Engineering community survey finds nearly half expect quantum computing to remain more than five years from chip-design relevance

A community survey on quantum computing finds roughly 45% of engineers believe the technology is still more than five years from affecting their chip work, while curiosity about it runs high.

22 Aug 2026
Generated imageThe Silicon Brief

The Silicon Brief - 22 August 2026

Today's digest: Broadcom eyes $60B in debt for an AI chip deal, Micron commits $10B to a Boise research lab, Wolfspeed's AI data center revenue more than doubles, Arista hits 12.8 Tb/s at Hot Interconnects, Kulicke & Soffa names a new CEO, and Washington directs federal agencies to prioritise semiconductor R&D.

22 Aug 2026
Generated imageDesign & EDA

Agentrys claims its Studio platform lets chip design teams assemble a custom multi-agent flow in 30 minutes

Agentrys says its Studio platform can stand up a custom multi-agent chip design flow in about 30 minutes, with a live demonstration planned for Hot Chips 2026 on 23-25 August.

21 Aug 2026
Generated imageDesign & EDA

Siemens EDA details Questa One's three-pillar AI update at DAC 2026

Siemens EDA briefed attendees at DAC 2026 on Questa One's latest AI-driven verification updates, covering faster engines, MCP-enabled inter-engine communication, and an Agentic Toolkit with five domain-scoped agents.

21 Aug 2026
Generated imageSemiconductors

Lam Research's Semiverse Solutions shows feedforward control lifting wafer pass rates from 61% to 97% in digital twin simulation

Lam Research's Semiverse Solutions used SEMulator3D digital twin simulation to show feedforward etch control raising wafer pass rates from 60.82% to 96.77% and improving Cpk 2.5x.

21 Aug 2026
Generated imageSemiconductors

Intel Foundry cuts carbon per wafer by up to 70% as AI demand pushes customers to scrutinise Scope 3

Intel's 2025-26 Corporate Responsibility Report shows a 70% carbon-per-wafer reduction and $999 million in green investment, directly lowering Scope 3 emissions for foundry customers.

21 Aug 2026
Generated imageSemiconductors

India's fifth SEMICON India opens 17 September with Semicon 2.0 and three plants already in production

SEMICON India 2026 runs 17-19 September in New Delhi with 500+ exhibitors and a new six-pillar Semicon 2.0 programme, as three Sanand facilities reach commercial production.

21 Aug 2026
Generated imageThe Silicon Brief

The Silicon Brief - 21 August 2026

Today's digest: TSMC confirms A16 mass production for Q4 2026, SIA names a new CEO, Samsung details SF2Z backside power for 2027, bond reliability emerges as a critical test bottleneck, and TSMC's Arizona second fab moves to equipment installation.

21 Aug 2026
Generated imageDesign & EDA

Quadric schedules three conference appearances to demonstrate Chimera GPNPU between 23 August and 24 September 2026

Quadric will appear at HotChips, AI Infra Summit, and Embedded World North America between 23 August and 24 September 2026 to demonstrate its Chimera GPNPU processor IP.

20 Aug 2026
Generated imageDesign & EDA

ESD Alliance schedules a Gen-AI for chip design and security webinar for 10 September 2026

The ESD Alliance's Savage on Security series returns on 10 September 2026, examining how multi-agent LLM systems will automate SoC design and security verification.

20 Aug 2026
Generated imageSemiconductors

Nordson argues wafer-mapped sampling must replace static bond-test strategies as interconnects shrink to a few microns

Nordson's Semiconductor Engineering analysis shows why static bond-test sampling is failing advanced packaging, and how dynamic wafer mapping is taking its place.

20 Aug 2026
Generated imageSemiconductors

NVIDIA, Google, and Microsoft push 800 VDC into AI data centers through OCP, targeting 2 MW per rack row by 2027

NVIDIA, Google, and Microsoft are formalising 800 VDC as the power standard for megawatt-scale AI racks, with more than 80 ecosystem companies already building to the OCP specification.

20 Aug 2026
Generated imageSemiconductors

AI data centers are splitting inference across CPUs, GPUs, and RDUs to cut token cost

A Semiconductor Engineering roundtable finds that heterogeneous clusters - not faster GPUs alone - are the primary lever for reducing AI inference token cost in 2026.

20 Aug 2026
Generated imageThe Silicon Brief

The Silicon Brief - 20 August 2026

Today's digest: Samsung locks its 1.4 nm node to 2029, Intel closes a $20 billion equity raise, NVIDIA turns compute into a Wall Street asset class, Micron opens a $250 million AI venture fund, and bond reliability emerges as the critical vulnerability in high-density semiconductor test.

20 Aug 2026
Generated imageDesign & EDA

Applied Materials argues AI energy efficiency requires co-optimization from chip materials to system architecture

At the OCP APAC Summit on 11-12 August 2026, Applied Materials' Subi Kengeri warned that AI's energy bottleneck cannot be solved at any single layer of the stack.

19 Aug 2026
Generated imageDesign & EDA

PDF Solutions redesigns Exensio around LLM agents and scalable analytics in its Aurora architecture

PDF Solutions has unveiled Exensio Aurora, a reimagined platform architecture combining scalable analytics, a semiconductor semantic knowledge graph, and on-premise LLM agents for manufacturing intelligence.

19 Aug 2026
Generated imageSemiconductors

Coherent ships 300 mm SiC substrate samples to AI semiconductor partners

Coherent began sampling 300 mm high-thermal-conductivity SiC substrates to AI chip customers on 17 August 2026, targeting a 25% heat-spreading improvement over current solutions.

19 Aug 2026
Generated imageSemiconductors

NVIDIA backs OpenAI's 8 IT-GW Ohio AI campus with a $105 billion guarantee and $1.5 billion equity stake

NVIDIA secured land, power and shell capacity at SB Energy's PORTS-Pike campus in Ohio for OpenAI, disclosing a $105 billion guarantee and a $1.5 billion equity investment on 17 August 2026.

19 Aug 2026
Generated imageSemiconductors

Nordson details how bond testing is shifting from sampling to data-driven process control in advanced packaging

Nordson's Semiconductor Engineering analysis shows bond testing moving beyond spot-checks toward AI-driven, wafer-mapped sampling as interconnect dimensions shrink to a few microns.

19 Aug 2026
Generated imageDesign & EDA

Rise Design Automation launches IPCreate and IPTransform platforms at DAC 2026, claiming one million gates per engineer per week

Rise Design Automation unveiled IPCreate and IPTransform at DAC 2026, adding an AI-powered spec-to-HLS-to-RTL flow that claims one million gates per engineer per week.

18 Aug 2026
Generated imageDesign & EDA

Washington State and UW-Madison propose an LSTM-driven framework that cuts voltage droop EDP by 76x in 2.5D PIM chiplet systems

Researchers from Washington State University and UW-Madison published ReVolt in August 2026, an LSTM-based runtime framework that eliminates voltage droop violations in 2.5D PIM chiplet platforms while cutting energy-delay product by 76x.

18 Aug 2026
Generated imageSemiconductors

Securus Monitoring brings GPS and remote alcohol testing to APPA's annual training institute in Chicago

Securus Monitoring is demonstrating BLUtag GPS and SoberTrack alcohol-testing devices at the APPA Annual Training Institute in Chicago, 16-19 August 2026, citing a 30% reduction in supervision failure.

18 Aug 2026
Generated imageThe Silicon Brief

The Silicon Brief - 18 August 2026

Today's digest: Intel and ASML confirm High-NA EUV in volume production as TSMC and Samsung defer to 2030, SK Hynix locks in a $500B Nvidia partnership, Nokia acquires NXP's Chandler fab for InP, Aixtron's optoelectronics orders surge 81%, and bond integrity emerges as the hidden reliability bottleneck in high-density test.

18 Aug 2026
Generated imageDesign & EDA

SemiWiki profiles Jerry Chen, who left Apple and Inphi to build an ultra-low-power edge AI chip startup in Taipei

SemiWiki's CEO interview with Jerry Chen traces his path from IC design at Intel and Apple to founding Upbeat Technology in 2021, where the UP201/UP301 RISC-V MCU and UPM01 MEMS sensor are now shipping.

17 Aug 2026
Generated imageDesign & EDA

SemiWiki interviews Aras CEO Leon Lauritsen on AI-native PLM and the digital thread

SemiWiki's CEO interview with Leon Lauritsen covers his path to leading Aras, the company's AI-native PLM strategy, and a new semiconductor industry accelerator shown at DAC 2026.

17 Aug 2026
Generated imageSemiconductors

Eight PQC signature candidates enter NIST's third round after tweaks deadline closes on 14 August 2026

NIST's third round of additional post-quantum digital signature evaluation opened with nine candidates in May 2026 and now runs with eight after AI cryptanalysis reshaped the field.

17 Aug 2026
Generated imageSemiconductors

Quanta Computer and Quantinuum sign a joint development agreement to industrialise large-scale quantum hardware

Quanta Computer and Quantinuum signed a collaborative development agreement on 13 August 2026 to co-develop the manufacturing infrastructure needed for fault-tolerant quantum computers at commercial scale.

17 Aug 2026
Generated imageThe Silicon Brief

The Silicon Brief - 17 August 2026

Today's digest: SMIC and Hua Hong hit record utilisation, Samsung repurposes its Giheung R&D line for 2 nm HBM base dies, TSMC confirms three straight years of CoWoS capacity doubling, Samsung defers High-NA EUV to 1 nm, and competition shifts from silicon to systems.

17 Aug 2026
Generated imageDesign & EDA

Tuple Technologies brings a three-product AI infrastructure stack to DAC 2026 booth 1569

Tuple Technologies showed its Stratos, Nitro, and Avestra products at DAC 2026 in Long Beach, targeting IC startups that need cloud EDA infrastructure without a dedicated IT or CAD team.

16 Aug 2026
Generated imageDesign & EDA

Bronco AI schedules a live SoC debug demonstration claiming root-cause analysis in under 15 minutes

Bronco AI is hosting a SemiWiki webinar to demonstrate its Debug Agent on a full-chip SoC, claiming autonomous root-cause analysis in under 15 minutes with a 70% first-pass success rate.

16 Aug 2026
Generated imageSemiconductors

IBM embeds GPT-5.6 and OpenAI Codex into its consulting platform in a new enterprise AI partnership

IBM and OpenAI announced a strategic partnership on 13 August 2026 to embed GPT-5.6, Codex, and ChatGPT Work into IBM Consulting Advantage, with a dedicated OpenAI Practice and expanded cybersecurity coverage.

16 Aug 2026
Generated imageSemiconductors

Anthropic's Claude Mythos forces HAWK out of NIST's third-round PQC signature process

Anthropic's Claude Mythos Preview halved HAWK's effective key strength in 60 hours on 28 July 2026, prompting the HAWK team to withdraw the scheme from NIST's third-round PQC signature evaluation within 24 hours.

16 Aug 2026
Generated imageThe Silicon Brief

The Silicon Brief - 16 August 2026

Today's digest: Lam Research commits $3 B to R&D lab expansion, Michigan and Imec launch Common Earth to cut rare-earth dependence, AI chiplet test complexity deepens, CPO test standardization stalls, and the industry reframes competition around systems rather than silicon.

16 Aug 2026
Design & EDA
Design & EDA

TSMC and NYCU engineer a 0.42 nm aluminum-oxide interface to unlock monolayer MoS₂ transistors

Researchers at TSMC Corporate Research and NYCU published a 0.42 nm Al₂O₃ buffer in Nature Electronics that resolves the gate-dielectric interface problem blocking practical 2D transistors.

15 Aug 2026
Generated imageDesign & EDA

ASML ships its first High-NA EUV production tool as maskless lithography gains ground in specialty fabs

ASML's EXE:5200B High-NA EUV scanner is now in volume production at Intel and Samsung, while multi-beam maskless tools carve out a parallel niche for advanced packaging and rapid prototyping.

15 Aug 2026
Generated imageSemiconductors

Sivers Semiconductors and SemiNex launch a $3.4 million InP light-source program for AI data center interconnects

Sivers Semiconductors and SemiNex announced a $3.4M InP light-source program on 13 August 2026, targeting co-packaged optics and wavelength-multiplexed links for AI data centers.

15 Aug 2026
Generated imageSemiconductors

Samsung reaches 80% yield on HBM4 six months into mass production, targeting 38% market share by year-end

Samsung's HBM4 yield climbed from below 60% to 80% within six months of mass production, four months ahead of plan, accelerating supply for Nvidia's Vera Rubin platform.

15 Aug 2026
Generated imageSemiconductors

MIT engineers build a stroke rehabilitation robot that learns physical assistance from therapists

MIT's Newman Laboratory has published a generative AI system that trains a KUKA robot to replicate the force and touch decisions of human physiotherapists during stroke rehabilitation.

15 Aug 2026
Generated imageThe Silicon Brief

The Silicon Brief - 15 August 2026

Today's digest: Samsung shifts legacy DRAM backend to Vietnam for HBM headroom, SK Hynix scouts US fab sites, Silicon Motion closes a $1.15 B bond, WSTS lifts its full-year forecast to $1.65 T, and the CHIPS Act R&D portfolio gets redirected.

15 Aug 2026
Generated imageDesign & EDA

AI energy demands are pushing hardware and software teams to design chips together again

Power and thermal constraints are forcing a new wave of hardware/software co-design across the chip industry, from custom AI ASICs to RISC-V embedded controllers.

14 Aug 2026
Generated imageDesign & EDA

Agentic AI reframes data-center design around the completed task, not the token

As AI agents replace single-turn inference with multi-step workflows, the critical performance metric shifts from tokens per second to cost per completed task - and the CPU moves back to center stage.

14 Aug 2026
Generated imageSemiconductors

Elektor extends ESP32 by Example course with AI coding tools and M5Stack hardware for its 26 August live session

Elektor Engineering Insights #62 on 26 August 2026 adds AI-assisted coding and M5Stack CoreS3 hardware to the ESP32 by Example learning course, with Villanova professor Jim Solderitsch.

14 Aug 2026
Generated imageSemiconductors

Ford previews a $25,000 compact crossover to dealers, targeting a 2029 launch at Hermosillo

Ford showed early mock-ups of an unnamed $25,000 compact crossover to dealers in Las Vegas during the week of 3 August 2026, with a planned 2029 production start at its Hermosillo plant in Mexico.

14 Aug 2026
Generated imageSemiconductors

IONNA scores 807 in JD Power's 2026 public charging study, leading all DC fast-charging networks

JD Power's 2026 EVX Public Charging Study finds DC fast-charging satisfaction up 12 points to 666/1,000, with IONNA, Mercedes-Benz, and Rivian topping the rankings.

14 Aug 2026
Generated imageThe Silicon Brief

The Silicon Brief - 14 August 2026

Today's digest: Nvidia ships CPO switches but testing standards lag, Samsung and SK Hynix signal rival HBM strategies ahead of Hot Chips, AI chiplet test complexity deepens, and measurement validity in multi-die packages.

14 Aug 2026
Generated imageDesign & EDA

NVIDIA and Duke researchers claim up to 97% DRV solve rate with self-supervised layout model SCALE

NVIDIA and Duke University published SCALE in July 2026, a self-supervised framework that boosts AI agents' sub-2 nm DRV solve rates by 12-25%, reaching up to 97% on 100 real cases.

13 Aug 2026