AI energy demands are pushing hardware and software teams to design chips together again

The semiconductor industry is in the middle of another swing toward specialization - and this time, energy is the forcing function. Semiconductor Engineering's analysis, published 14 August 2026, finds that hardware and software teams that once worked in isolation are being pushed into tighter co-design loops by the power and thermal demands of AI workloads, a shift that is reshaping EDA methodology, IP strategy, and processor architecture simultaneously^[1].

The wall-throwing era is over

For most of the past two decades, hardware and software development ran on separate tracks. A hardware team would build a platform, then hand it to an embedded software team to deal with. That model effectively ended more than two decades ago, according to Steve Roddy, chief marketing officer at Quadric^[1]. What replaced it was virtual prototyping - and that practice has since expanded to cover physical inputs and sensor interfaces in what is now called virtual twin modeling^[1].

The underlying dynamic is a familiar one. Tsugio Makimoto, then CTO at Sony, observed in the early 1990s that the electronics industry cycled between custom and programmable solutions approximately every ten years - a pattern now known as Makimoto's Wave. EDA tools have historically been a key driver of that pendulum, making customization progressively cheaper and more accessible with each cycle. The current swing toward custom ASICs carries its own twist, however: software iteration now moves faster than hardware, making co-design a perpetual catch-up exercise for chip architects^[1].

Energy and thermal pressure are the new forcing function

The common thread pulling teams toward co-design today is power. Arvind Srinivasan, design verification solutions engineer at Normal Computing, notes that abstraction layers between hardware and software stacks were built to manage developer complexity - but the need to squeeze optimization out of every part of the tool chain has grown acute for performance-sensitive AI workloads^[1].

That pressure shows up differently depending on where a chip sits in the system:

• At the data-center edge, AI agents running continuously mean designers can no longer plan for average power; peak power must be assumed at all times.
• At the embedded edge, battery and thermal budgets are tight enough that general-purpose cores cannot compete with workload-specific silicon.
• At the IP level, companies are designing hardware explicitly around customer workloads rather than offering generic compute blocks^[1].

RISC-V as a co-design lever

One concrete expression of the trend is the role RISC-V is playing in custom processor development. Sean Murphy, senior director of product at MIPS/GlobalFoundries, says IP companies are focusing on designing hardware around customer workloads and application focus, and that this is precisely where RISC-V is finding its differentiation^[1]. The architecture's extensibility lets teams add domain-specific instructions - vector, tensor, or matrix operations - without abandoning a common software toolchain. The MIPS S8200, now part of GlobalFoundries, tightly couples RISC-V application cores with AI engines and supports a software-first design philosophy that lets developers model inference workloads on a virtual platform before silicon exists.

System-level EDA tools, however, have not kept pace. Andy Meier, principal product marketing manager at Siemens EDA, points out that architecture - spanning both macro-level hardware decisions and micro-level implementation - is where tools still struggle most^[1]. Modern SoCs now integrate multiple compute fabrics, domain-specific accelerators, high-speed interconnect fabrics, and security features within a single package, all expected to operate across diverse thermal envelopes and manufacturing tolerances.

The next pressure point to watch is whether EDA vendors can close the gap between workload-level simulation and physical implementation fast enough to keep pace with AI model iteration cycles - which, unlike hardware, show no sign of slowing down.