Applied Materials argues AI energy efficiency requires co-optimization from chip materials to system architecture

At the OCP APAC Summit in Taipei on 11-12 August 2026, Applied Materials Corporate Vice President Subi Kengeri delivered a keynote framing energy efficiency - not raw transistor count - as the binding constraint on AI's next phase of growth^[1]. The central argument: no single layer of the semiconductor stack can solve the problem alone, and the industry must co-optimize simultaneously from materials and process through packaging, architecture, and system software.

The energy bottleneck that Moore's Law cannot fix

Kengeri warned that the artificial intelligence boom faces a critical bottleneck in energy efficiency. The concern is structural. AI and HPC performance demands grew nearly ten times over the two years from 2021 to 2022, a pace that Moore's Law alone cannot sustain. Scaling transistors smaller still delivers some gains, but the power-per-operation curve is no longer falling fast enough to keep pace with model size and inference volume.

Applied Materials CEO Gary Dickerson had already flagged the revenue dimension of this shift. On a 12 February 2026 earnings call, Dickerson said global semiconductor industry revenues could reach $1 trillion in 2026, several years earlier than previously predicted. Kengeri's OCP APAC keynote put the engineering challenge behind that number in sharper relief: reaching and sustaining that scale requires efficiency gains that compound across every layer of the stack, not just at the leading edge of lithography.

What co-optimization means in practice

Kengeri's framing - "systems to materials" - describes a design philosophy in which decisions at the materials and process level are made with full visibility into system-level power and performance targets, and vice versa. Applied Materials' OCP APAC Summit presentations in Taipei and its newly announced research collaboration with UC Berkeley at the EPIC Center underscore the company's focus on accelerating semiconductor materials and process innovation for AI computing in a manufacturing-relevant setting. By giving UC Berkeley researchers access to industry-scale tools, the EPIC Center is designed to shorten the path from lab discovery to high-volume chip production.

The practical levers Kengeri pointed to span several domains:

• Materials and process: new gate dielectrics, contact metals, and interconnect materials that reduce resistive losses at advanced nodes
• Advanced packaging: heterogeneous integration of logic, memory, and I/O dies to cut the energy cost of data movement
• Architecture: chiplet-based designs that allow each function to be fabricated at its optimal process node
• System software: workload scheduling and power management that exploit hardware headroom rather than leaving it idle

Applied Materials has announced a new innovation partnership with TSMC to accelerate the development and commercialization of semiconductor technologies required for the next era of AI. Working together at Applied's EPIC Center in Silicon Valley, the companies will co-innovate to advance materials engineering, equipment innovation, and process integration technologies designed to deliver energy-efficient performance from the data center to the edge.

Where the argument lands in the EDA flow

The co-optimization thesis has a direct implication for design tools. If power budgets must be met across the full stack, then EDA flows need to carry materials-level constraints - thermal conductivity, contact resistance, interconnect parasitics - into early architectural decisions rather than treating them as sign-off checks. At DAC 2026 in Long Beach, Synopsys announced fully autonomous, long-running agentic workflows for chip and electronics system design, enabled by NVIDIA Nemotron on NVIDIA's accelerated computing platform, headlined by a design verification agent that orchestrates the entire chip verification cycle. Whether those agents can ingest process-level constraints early enough to close the loop Kengeri described remains an open question.

The next signal to watch is how Applied Materials' EPIC Center partnerships - with TSMC, UC Berkeley, Stanford, and Advantest - translate into process recipes and equipment specifications that EDA vendors can model. If materials data reaches design tools earlier in the flow, the co-optimization argument moves from keynote aspiration to engineering practice.