ESD Alliance schedules a Gen-AI for chip design and security webinar for 10 September 2026

The ESD Alliance has announced the next instalment of its Savage on Security webinar series, titled "Gen-AI for Chip Design & Security," scheduled for Thursday, 10 September 2026, at 9 am PDT.^[1] The session will examine how multi-agent intelligent assistant systems will be architected to automate and augment SoC design and security verification.^[1]

The speakers and their background

The webinar is hosted by Warren Savage, a researcher at the University of Maryland's Applied Research Laboratory for Intelligence and Security (ARLIS).^[1] Savage founded IPextreme in 2004, a semiconductor IP commercialisation company that was sold to Silvaco in 2016. Before that, he held technical and executive roles at Fairchild, Tandem Computers, and Synopsys.

Joining him is Mark M. Tehranipoor, Intel Charles E. Young Endowed Chair Professor and chair of the Department of Electrical and Computer Engineering at the University of Florida, where he also directs the Florida Institute for Cybersecurity (FICS) Research. Tehranipoor's group has been among the most active in applying LLMs to hardware security, with recent work spanning emulation-based SoC fuzzing, LLM-assisted security asset identification, and automated assertion generation.

What the session will cover

The central argument is that monolithic LLMs are insufficient for the complexity of modern SoC security work.^[1] The webinar will argue that multi-agent architectures - where specialised models collaborate across distinct sub-tasks - are the right structural answer.^[1] The University of Florida group's published SV-LLM framework illustrates the approach in practice: it integrates separate agents for verification question answering, security asset identification, threat modelling, test-plan and property generation, vulnerability detection, and simulation-based bug validation, with each agent using a different learning paradigm such as in-context learning, fine-tuning, or retrieval-augmented generation (RAG).

The broader design-automation angle is equally significant. Beyond security, the session will address how LLMs can support architectural reasoning, specification refinement, and design-space exploration - tasks that have historically required senior engineers working across long cycles.

Key themes the webinar is expected to address:

• Multi-agent system architecture for SoC design and verification
• LLM capabilities beyond code generation: architectural reasoning and vulnerability analysis
• Security verification automation from threat modelling through bug validation
• What "trusted silicon" means when AI generates or checks the design

Why this matters for EDA teams

The Savage on Security series sits within the ESD Alliance's broader push to put hardware security on the same footing as functional correctness in the design flow. The June 2026 ESD Alliance Executive Outlook, held at Cadence's San Jose headquarters, had already flagged agentic AI as the dominant near-term inflection point for chip design and verification teams. The September webinar narrows that lens to security specifically - a domain where the cost of a missed vulnerability is measured not in re-spins but in compromised devices in the field.

The session is open to SemiWiki readers. Whether the multi-agent framing translates from research prototypes into production EDA flows - and on what timeline - is the question worth pressing during Q&A.