Quadric schedules three conference appearances to demonstrate Chimera GPNPU between 23 August and 24 September 2026

Quadric, the Burlingame, California processor IP licensor, is appearing at three industry conferences between 23 August and 24 September 2026 to demonstrate its Chimera general-purpose neural processing unit (GPNPU) to chip architects, SoC developers, and embedded engineers^[1]. The tour follows the company's July 2026 announcement that its Series C financing has reached $46 million, with total capital raised now standing at $90 million after a second close led by the International Finance Corporation.

Three stops, three audiences

The schedule runs as follows:

• HotChips 2026 (HC38) - 23-25 August, Stanford University, Stanford, California. Quadric is a sponsor and will be present in the expo area^[1]. The venue draws chip architects and SoC developers who want to examine architectural trade-offs at depth, making it a natural setting for discussions about how Chimera combines neural-network acceleration with programmable scalar, vector, and matrix processing in a single unified pipeline^[1].
• AI Infra Summit - 15-17 September, Santa Clara Convention Center, Booth 746^[1]. Quadric CTO Nigel Drego is scheduled to present "Take Control: A Processor Designed for On-Device AI" on 16 September 2026 at 3:00-3:20 PM. The summit, now in its ninth year, draws around 8,000 attendees focused on the compute, networking, and storage layers that underpin large-scale AI deployment.
• Embedded World North America - 22-24 September, Anaheim Convention Center, Anaheim, California. Software Architect Mike Leonard will present "Porting Vision-Language-Action Models to Embedded NPUs: Architectural Requirements and Optimization Techniques" at 10:25 AM as part of the Embedded Model Deployment technical track^[1].

What Chimera is being asked to demonstrate

The three venues each probe a different pressure point for on-device AI silicon. At HotChips the conversation is architectural: how Chimera's hybrid Von Neumann and 2D SIMD design unifies matrix, vector, and scalar operations in one execution pipeline, removing the need for a companion CPU or DSP. At the AI Infra Summit the focus shifts to deployment economics - specifically the case for running inference locally rather than routing every query to a cloud cluster. At Embedded World North America the question is physical AI: whether a programmable NPU can handle the quantization complexity and mixed compute-and-bandwidth demands of vision-language-action (VLA) models without a silicon respin when operators change.

Chimera GPNPU cores scale from 1 TOPS to 864 TOPS and are available in commercial-grade and automotive safety-enhanced (ASIL-ready) configurations. The architecture runs any ONNX-captured model and allows custom operators to be written in C++, which Quadric claims eliminates the need to wait for a new chip when a model introduces unsupported operations.

Commercial backdrop

Quadric reported that product revenue more than tripled in 2025 compared with 2024 and that the company reached profitability before announcing the Series C second close in July 2026. Licensees now span automotive, edge LLM, AI PCs, and autonomous driving, with humanoid robotics and wearables cited as incoming demand areas.

The conference run comes at a moment when fixed-function NPU IP is under pressure from model churn: operators that do not exist today will appear in next year's model releases, and a processor that cannot be updated in software forces a respin. Whether Quadric's programmability argument translates into further design wins across the three audiences it is targeting this autumn is the number to watch.