Intel Foundry cuts carbon per wafer by up to 70% as AI demand pushes customers to scrutinise Scope 3
Intel's 2025-26 Corporate Responsibility Report shows a 70% carbon-per-wafer reduction and $999 million in green investment, directly lowering Scope 3 emissions for foundry customers.

Intel Foundry's 2025-26 Corporate Responsibility Report, published in June 2026, puts a concrete number on what lower-carbon semiconductor manufacturing means for customers: up to a 70% reduction in carbon footprint per wafer compared with a conventional grid-energy baseline[1]. That figure matters because, for fabless chip designers and hyperscale cloud operators, wafer production typically sits inside their Scope 3 inventory rather than their own operational footprint.
Why foundry emissions land in customer Scope 3
Greenhouse gas emissions are reported in three tiers. Scope 1 covers a company's direct emissions; Scope 2 covers purchased energy; Scope 3 covers indirect emissions across the value chain - suppliers, manufacturing partners, logistics, and product use[1]. Because chip manufacturing is typically performed by foundry partners, emissions generated during wafer production are generally reflected in customers' Scope 3 inventories rather than their direct operational footprint[1]. As AI infrastructure scales and sustainability disclosures tighten, that accounting detail is becoming a procurement consideration.
What Intel Foundry reported for 2025
The renewable electricity headline is the foundation of the per-wafer figure. In 2025, Intel achieved 100% renewable electricity across its U.S., European, Israeli, Malaysian, Vietnamese, and Chinese manufacturing sites, bringing the global total to 99%[1]. The cumulative effect is significant: nearly 85% of Intel's Scope 1 and Scope 2 emissions over the past decade have been avoided through renewable energy and efficiency investments[1], and Scope 1 and Scope 2 GHG emissions are down 16% versus the 2019 baseline[1].
Beyond energy, the report records:
- Approximately 11.2 billion gallons of water conserved in 2025 through operational improvements and community partnerships[1], with net positive water status achieved in the United States, India, and Costa Rica
- Approximately 69% of manufacturing waste streams reused, recovered, or recycled[1]
- $999 million allocated to green projects between 2021 and 2025, covering emissions avoidance, energy and water savings, and waste diversion[1]
Process technology as a second lever
Sustainable manufacturing operations address the carbon embedded in making a chip. Process efficiency addresses the carbon emitted when that chip runs in a product - the downstream Scope 3 that customers carry in their own inventories.
Intel 18A, which entered production in 2025, delivers up to 18% higher performance at iso-power or up to 38% lower power at iso-performance compared with Intel 3, alongside approximately 30% greater chip density[1]. The follow-on Intel 14A is expected to deliver a further 15-20% performance gain at iso-power or 25-35% lower power at iso-performance[1]. Denser, more power-efficient chips mean fewer devices needed per workload and lower energy draw per operation - both of which reduce the Scope 3 emissions customers report from product use.
Intel is also working upstream: in 2026 the company is engaging its top suppliers to submit validated GHG reduction goals and actionable plans toward a net-zero upstream Scope 3 target by 2050.
The long-term targets - net-zero Scope 1 and Scope 2 by 2040, net-zero upstream Scope 3 by 2050 - set the trajectory[1]. The near-term test is whether the 18A-P risk-production ramp and the supplier engagement programme translate the per-wafer carbon gains into verified reductions that customers can book in their own sustainability disclosures.
Written by Electronics Insider's automated desk from the sources above and published automatically. How we work.
Related
Design & EDASignaloid founder Phillip Stanley-Marbell steps down from Cambridge chair to run probabilistic computing startup full-time
SemiWiki's CEO interview with Phillip Stanley-Marbell traces his path from Bell Labs and Apple to founding Signaloid, a Cambridge spinout whose C0-ASIC targets 1000× performance-per-watt gains.
22 Aug 2026TSMC's COUPE co-packaged optics platform enters production in the second half of 2026
TSMC's Compact Universal Photonic Engine moves from qualification to volume production in H2 2026, promising 2x power efficiency and 10x lower latency over pluggable optics.
22 Aug 2026
SemiconductorsSemiconductor Engineering frames energy efficiency as the defining constraint for AI computing through 2030
Data center electricity is set to nearly double to 945 TWh by 2030, making energy efficiency the central strategic challenge - and opportunity - for every company deploying AI at scale.
22 Aug 2026