NVIDIA and Duke researchers claim up to 97% DRV solve rate with self-supervised layout model SCALE

Researchers from NVIDIA and Duke University posted a paper in July 2026 describing SCALE, a self-supervised framework for fixing local place-and-route (P&R) design-rule violations (DRVs) at sub-2 nm nodes^[1]. Tested on 100 real sub-2 nm cases, the system raised state-of-the-art AI agents' solve rates by 12-25 percentage points, reaching up to 97%^[1].

Why local DRV fixing is breaking down at advanced nodes

As semiconductor manufacturing advances toward sub-2 nm nodes, local P&R DRV fixing is increasingly limited by complex rule interactions, dense multi-layer routing geometries, and foundry-specific constraints^[1]. General-purpose vision-language models (VLMs) cannot fill the gap: diagnosing DRC violations from layout imagery demands precise geometric reasoning and foundry-specific rule knowledge that standard VLM training does not provide^[1].

The result is a data-labelling bottleneck. Annotated layout-violation pairs are scarce, and manually tagging them at sub-2 nm is expensive and slow. SCALE is designed to sidestep that bottleneck entirely.

How SCALE generates its own training data

The framework works in two stages^[1]:

• Self-supervised pre-training. Multi-layer layout geometry is serialised into structured text. A fine-tuned language model then learns to reconstruct randomly masked polygons from the surrounding back-end-of-line (BEOL) context - with no violation labels required.
• Synthetic data generation. At inference, natural-language rule constraints and high-temperature sampling steer the model toward diverse, violation-prone layout variants. An industrial signoff DRC checker validates each variant, producing DRC-annotated layout-violation pairs automatically.

Those pairs are used to fine-tune a domain-adapted DRC vision-language model (DRC-VLM). At repair time, the DRC-VLM analyses a local GDS region surrounding each violation site and proposes rule-aware geometric guidance - which is then handed off to a downstream AI agent to execute the actual fix^[1].

What the benchmark shows

The paper evaluates SCALE on 100 real sub-2 nm cases covering enclosure, spacing, width, and color-spacing violations^[1]. Across that set, the DRC-VLM guidance lifted agent solve rates by 12-25 percentage points, with the best result reaching 97%^[1]. The authors note that general VLMs fail at the prerequisite violation-localisation task, which is why the domain-adapted model is necessary before any repair agent is invoked.

The nine-person author list spans NVIDIA Research (Santa Clara and Austin) and Duke University, with Chia-Tung Ho, Haoyu Yang, and Guanglei Zhou listed as equal contributors and corresponding authors^[1]. The paper is available as arXiv preprint 2607.21850.

The immediate question for EDA tool vendors is whether the synthetic-data pipeline generalises across foundry rule decks - the paper tests one sub-2 nm technology, and rule sets differ significantly between foundries. Whether the self-supervised pre-training transfers to a new node without rerunning the full generation stage will determine how practical SCALE is as a production flow component rather than a research prototype.