SIA and Deloitte find semiconductors account for 95% of an AI server rack's value in June 2026 teardown study

A June 2026 report from the Semiconductor Industry Association (SIA) and Deloitte has put hard numbers on what the industry has long suspected: the AI data center buildout is, at its core, a semiconductor procurement contest. A virtual teardown of a state-of-the-art AI server rack found that chips account for more than 95% of its content value, and that a single rack contains over 4,500 packaged chips and approximately 20,000 semiconductor dies.^[1]

The report, titled Powering AI: The Semiconductor Ecosystem at the Foundation of Data Centers, was published on 1 June 2026. It is the primary source behind the SemiWiki white paper that surfaced this week, and it frames the AI infrastructure race not as a software or model story but as a full-stack chip supply challenge.

What is actually inside a rack

The teardown maps every tray in a leading AI server rack. The chip categories span:

• Advanced logic: AI accelerators, ASICs, FPGAs, CPUs, DPUs, and networking chips
• Memory: HBM, DRAM, SRAM, and NAND flash
• Analog and foundational: power chips, transceivers, controllers, and sensors

Semiconductor buying makes up more than 50% of the total capital expenditure required to build and operate an AI data center, the report finds. That figure reframes the economics: the data center construction boom is, in spending terms, mostly a chip order.^[1]

Memory is the constraint that shapes topology

The chip count alone does not capture where the design pressure is sharpest. Experts at Semiconductor Engineering's recent roundtable on AI data center architecture identified memory bandwidth and interconnect orchestration as the two dominant bottlenecks - not raw compute.^[3] As AI models grow, the cost and utilization of HBM, and how it is paired with dynamic context memory, become critical factors for GPU-based systems.^[3]

That pressure is driving a format shift in system memory. SK hynix began mass production of a 192 GB SOCAMM2 module on 20 April 2026, targeting Nvidia's Vera Rubin platform. The module is based on LPDDR5X built on the 1cnm process and claims more than double the bandwidth and over 75% better power efficiency compared with conventional RDIMM.^[2] Micron separately announced a 256 GB SOCAMM2 variant in March 2026, claiming 2.3x faster time-to-first-token for long-context LLM inference versus standard DDR5 configurations.

Interconnect topology determines what parallelism is possible

Beyond memory, the roundtable discussion highlighted that the choice of parallelism strategy - tensor parallel, data parallel, pipeline parallel, or context parallel - imposes distinct requirements on network topology.^[3] Tensor-parallel workloads demand all-reduce collectives, which makes high-bandwidth scale-up fabric such as NVLink critical; pipeline-parallel jobs are more tolerant of lower-bandwidth point-to-point links. GPU density per rack has increased roughly 6x from 2021 to 2026, from 8-16 GPUs per rack to 72+ in the GB200 NVL72, compressing more of the critical fabric inside a single rack enclosure and reducing the penalty of cross-rack hops.

The SIA-Deloitte figures give the investment context: government and industry are projected to invest over $4 trillion in new data center infrastructure through 2028, with up to $2.8 trillion of that flowing to semiconductors.^[1] The AI data center market is projected to grow at a CAGR of 88.8% between 2022 and 2028, with a still-elevated 56.3% CAGR expected from 2025 to 2028 even after the initial generative AI surge. The implication for design teams is that every architectural decision - memory form factor, interconnect standard, accelerator topology - is being made against a backdrop of sustained, large-scale capital commitment that shows no sign of plateauing before the end of the decade.