Signaloid founder Phillip Stanley-Marbell steps down from Cambridge chair to run probabilistic computing startup full-time

SemiWiki has published a CEO interview with Phillip Stanley-Marbell, founder of Signaloid, a University of Cambridge spinout building hardware for uncertainty-tracking computation^[1]. The interview arrives as the company ships its first silicon: the C0-ASIC, taped out with TSMC in partnership with IC-Link by imec and Cadence, is projected to deliver up to 1000× better performance-per-watt in key physical AI workloads, with engineering samples due to the first customer in Q3 2026.

From Cambridge chair to full-time CEO

Stanley-Marbell stepped down from his full professorship - the Chair of Physical Computation in the Electrical Engineering Division at the University of Cambridge - in September 2025 to lead Signaloid as a full-time executive^[1]. His academic career at Cambridge began in 2017, when he joined as an assistant professor; he received tenure in 2020 and was promoted to full professor in 2022. Before academia, he held positions at Bell Labs, IBM Research Zurich, Apple, and MIT, and completed his PhD at Carnegie Mellon University.

He incorporated Signaloid in 2019, self-funding it for two years before raising angel investment in 2021 and completing a seed round in January 2023. The company has since grown to serve more than 3,000 users across 18 countries, with hardware available through Mouser Electronics and DigiKey.

What the technology does

Signaloid's core product is UxHw (Uncertainty Hardware), a distribution-extended compute architecture that tracks statistical probability distributions through arithmetic operations, transparently to the running application. The practical effect is that workloads which would ordinarily require repeated Monte Carlo sampling - particle filters, sensor fusion, quantitative finance simulations - can instead be executed in a single pass.

Benchmarks on the cloud platform, integrated with AWS, show the following claimed speedups against Intel Xeon-class hardware at equivalent power:

• Over 580× for Heath-Jarrow-Morton swaptions pricing
• Over 430× for Value at Risk on geometric Brownian motion processes
• Over 80× for radiation transport simulations
• Over 600× for infrared sensor data analysis

Named cloud customers include Boeing and CERN. The UxHw technology and its implementation are covered by a portfolio of over 90 intellectual property filings in the US, China, Taiwan, Japan, and the EU.

The C0-ASIC and ARIA backing

The C0-ASIC - internally named C0-Dreadnought - is the first silicon implementation of UxHw. The UK Advanced Research and Invention Agency (ARIA) commissioned the chip for evaluation in randomized numerical linear algebra and probabilistic computing workloads as part of its Scaling Compute programme. FPGA-based systems implementing the ASIC's RTL design are also under discussion for deployment in the UK and Switzerland later in 2026.

Cadence supplied Artisan SRAM memories for the design; IC-Link by imec managed the path to TSMC production. The chip is targeted at robotics, physical AI, aerospace, and quantitative finance - workloads where uncertainty is inherent in the input data and where conventional floating-point pipelines discard distributional information at every arithmetic step.

The next milestone to watch is delivery of engineering samples in Q3 2026 and whether ARIA's evaluation of second-order methods on the C0-ASIC produces publishable benchmark results - data that would give the broader design community its first independent view of the architecture's performance claims at silicon level.