The Silicon Brief - 12 August 2026

Today's edition covers five developments chip professionals need before their first meeting: a landmark SIA quarterly sales print, the live impact of Japan's tungsten hexafluoride production halt, TSMC's accelerated 1.4 nm construction timeline, a reported TSMC move into EMIB-style packaging, and new scrutiny of HBM as a 3D assembly yield testbed.

SIA reports $403.3 billion in Q2 2026 global chip sales, with June up 123.6% year-on-year. The Semiconductor Industry Association announced on 6 August 2026 that global semiconductor sales reached $403.3 billion in the second quarter of 2026, a 35.1% increase over Q1, with June alone hitting $134.5 billion - a 123.6% year-on-year gain. SIA president John Neuffer said global chip sales are now on track to exceed $1.5 trillion for the full year. For procurement and planning teams, the print confirms that AI-driven demand is not softening: the sequential acceleration from Q1 to Q2 is the clearest signal yet that the current cycle has further to run.

Japan's permanent halt of tungsten hexafluoride production is now in effect, removing roughly a quarter of global supply. Kanto Denka Kogyo and Central Glass permanently ceased WF₆ production on 1 July 2026, having formally notified Samsung, SK Hynix, and TSMC in April. The shutdown was triggered by China's export controls on tungsten, which cut Japan's access to high-purity tungsten powder - the feedstock that accounts for 60-70% of WF₆ production cost. WF₆ prices surged more than 200% year-on-year ahead of the halt, and the combined Japanese capacity loss amounts to approximately 2,200 tons per year, or roughly 25% of global supply. WF₆ is the only commercially viable precursor for depositing tungsten films in sub-7 nm logic, HBM, and 3D NAND - and qualifying a new supplier takes 18 to 24 months. Fabs that have not already locked in alternative sources face a structural cost and yield risk through at least mid-2028.

TSMC's $49 billion 1.4 nm fab in Taichung is running ahead of schedule, with first silicon now targeted for April 2027. Construction at the Central Taiwan Science Park site began in November 2025, and the Commercial Times reported on 3 August 2026 that the project is ahead of its original timeline. Trial production could begin in Q3 2027, with mass production targeted for mid-2028. The process will use the second generation of TSMC's gate-all-around transistor but will not require ASML's High-NA EUV tool - a meaningful cost and supply-chain advantage. Intel is targeting 1.4 nm risk production in the second half of 2027, and Samsung is aiming for 2029, so an accelerated TSMC ramp would extend the foundry leader's execution gap at the leading edge.

TSMC is reportedly developing an EMIB-like chip-packaging technology to rival Intel Foundry, with Nvidia evaluating Intel's version for a future processor. According to The Information, TSMC is working on a technology internally called "EMIB Like," partnering with Taiwan's Kinsus Interconnect Technology on the project. Intel's Embedded Multi-die Interconnect Bridge has been a key differentiator for Intel Foundry in attracting chiplet customers. The report also noted that Nvidia - currently TSMC's largest CoWoS customer - is evaluating Intel's EMIB for a future product, a signal that packaging technology is becoming a competitive battleground independent of wafer node. If TSMC launches a credible EMIB equivalent, it would close one of the few remaining technical gaps that Intel Foundry has used to differentiate its offering.^[2]

HBM is emerging as the primary testbed for 3D assembly yield, and the complexity is creating bottlenecks across the supply chain. As AI accelerators move to interposer-based modules that co-integrate compute die, HBM stacks, and I/O die, the test challenge has grown sharply.^[1] "HBM testing can be a major bottleneck due to the complexity of test program development," said Quoc Phan, technology enablement manager of 3DIC DFT and yield at Siemens EDA.^[1] The difficulty compounds once known-good components are assembled into a multi-die package: thinning, bonding, underfill, and neighboring dies introduce stress conditions that were absent when individual components were measured, opening new failure modes that pre-assembly test cannot catch.^[3] For test engineers and OSAT partners, the implication is that HBM qualification is no longer a memory problem - it is a systems integration problem that requires fault models and test algorithms built for the assembled package, not the individual die.^[1]