Synopsys hosts TetraMem and ANAFLASH at DAC 2026 to show compute-in-memory chips attacking the AI weight-movement bottleneck

On 28 July 2026, Synopsys ran an exhibitor forum session at DAC in Long Beach titled "How Silicon Startups are Addressing the AI Memory Gap," hosted by Vikram Bhatia, Head of Cloud Product Management at Synopsys^[1]. Two startups took the stage: TetraMem, presenting through Wenbo Yin, SVP of IC Design, and ANAFLASH, presenting through R. Scott Hills, VP of Business Development^[1]. The session's premise, stated plainly in the conference program, is that memory is currently the biggest bottleneck for AI hardware - HBM bandwidth and capacity in the datacenter, and the energy cost of moving weights at the edge.

The problem both companies are solving

Conventional AI inference pipelines move trained model weights from NAND flash into DRAM and then into on-chip SRAM before any computation can begin. In that architecture the trained model is stored in NAND, copied to DRAM, and then processed once copied to SRAM in a processor - a chain that results in a significant performance bottleneck, consumes large amounts of power, and requires substantial DRAM. Both companies attack this by running multiply-accumulate operations inside the memory array itself, so model weights never make the trip to a separate processor^[1].

The datacenter race is crowded and well-funded, but the edge is the next frontier for AI hardware, and a faster bus does not address the problem there. The session focused on a new class of startups attacking the problem at its root, by computing directly inside non-volatile memory on mature, standard CMOS nodes.

TetraMem: multi-level RRAM on 22 nm

TetraMem was founded in 2018 and shipped its first multi-level ReRAM chip for in-memory compute (IMC) in 2026, backed by more than 120 patents^[1]. The company has completed more than ten silicon tape-outs using its IMC technology^[1]. The classic multiply-accumulate step happens inside the RRAM crossbar array, bypassing the high-bandwidth IO path altogether^[1].

The chip shown at DAC is the MLX200. TetraMem announced the successful tape-out, manufacturing, and initial silicon validation of the MLX200 platform - a 22 nm multi-level RRAM-based analog IMC system-on-chip - in May 2026. The platform integrates multi-level RRAM arrays with mixed-signal compute engines to enable high-throughput vector-matrix operations within memory. The MLX200 and MLX201 platforms target voice and audio processing, wearable devices, IoT systems, and always-on sensing; evaluated sampling is expected to begin in the second half of 2026.

For its design flow, TetraMem used Synopsys Cloud to achieve quick system bring-up in minutes, speed RTL verification simulation, and avoid additional CAD engineers and IT infrastructure^[1].

ANAFLASH: two chips, two approaches to eliminating model traffic

ANAFLASH presented two products at the session. The first is the Reflex Computing Unit (RCU), which mimics sensory and motor neurons by coupling a low-power AI inference engine tightly with FLASH memory^[1]. The approach eliminates AI model traffic by keeping weights resident in non-volatile storage next to the compute engine^[1].

ANAFLASH has developed an AI MCU using its proprietary standard logic-compatible embedded flash technology on Samsung Foundry's 28 nm process, integrating zero-standby-power weight memory based on its Logic-EFLASH technology - a cost-effective and energy-efficient design for battery-powered smart edge devices.

The second product is Legato-Logic, a time-domain neural network processor IP that ANAFLASH gained through its February 2025 acquisition of Legato Logic^[1]. Legato-Logic eliminates excessive data traffic, allowing low-power and low-latency execution of large AI models right where they are stored; it uses standard logic and a time-domain compute-in-memory technology that integrates into any type of memory. Following the integration of the Legato Logic team, ANAFLASH now offers both compute-near-flash and compute-in-flash approaches that can be integrated in a standard logic or NAND flash process without any process modification.

What to watch

Both companies are still in early commercialisation. TetraMem's MLX200 evaluation kits are targeted for the second half of 2026, and ANAFLASH is showing its Legato-Logic IP at DAC and FMS 2026. The more telling signal will be whether either company can demonstrate customer silicon - not just evaluation kits - on a disclosed production schedule. The Synopsys Cloud angle is also worth tracking: both startups used cloud EDA to tape out without dedicated CAD teams, a model that other resource-constrained compute-in-memory startups are likely to follow.