TSMC and NYCU engineer a 0.42 nm aluminum-oxide interface to unlock monolayer MoS₂ transistors

Researchers at National Yang Ming Chiao Tung University (NYCU) and TSMC Corporate Research published a paper in Nature Electronics on 31 July 2026 describing a monolayer MoS₂ transistor whose gate stack includes a 0.42 nm aluminum-oxide buffer layer - one of the thinnest gate-dielectric interfaces demonstrated on a CVD-grown 2D semiconductor^[1].

The problem the interface was designed to solve

A monolayer of MoS₂ is naturally about 0.7 nm thick, giving it tighter electrostatic control at very small dimensions than silicon can offer. The catch is its van der Waals surface: chemically inert and free of dangling bonds, it gives conventional atomic-layer deposition (ALD) nothing to nucleate on cleanly. The result is a rough, non-uniform dielectric with pinholes that scatter electrons and allow leakage current - the two failure modes that have kept 2D transistors out of production for years.

Previous attempts addressed this by switching dielectric materials, using molecular seed layers, or trying alternative deposition routes. Although those approaches produced improvements, achieving low equivalent oxide thickness, strong electrostatic control, and high carrier mobility simultaneously remained difficult, especially on wafer-scale CVD-grown MoS₂.

What the team built

Rather than change the semiconductor or the dielectric, the NYCU-TSMC team redesigned the interface between them:

1. An ultrathin epitaxial aluminum layer was deposited directly onto CVD-grown monolayer MoS₂.
2. The aluminum was carefully oxidized, forming a 0.42 nm Al₂O₃ buffer - smooth, conformal, and chemically stable.
3. A high-κ hafnium oxide gate dielectric was deposited on top of that buffer.

The combined stack achieved an equivalent oxide thickness of approximately 1 nm, a standard benchmark for next-generation devices. The resulting transistors showed low leakage current and minimal hysteresis. For 100 nm channel lengths, the devices reached a maximum transconductance of 0.45 mS μm⁻¹.

Because the MoS₂ was grown by CVD rather than mechanically exfoliated from a bulk crystal, the result is directly relevant to wafer-scale processing - a distinction that separates it from many laboratory demonstrations.

Where this fits in the broader 2D-material push

The NYCU-TSMC paper is not an isolated result. In June 2026, imec, ASML, and TSMC jointly presented a scalable 300 mm integration route for 2D-material transistors at the IEEE/JSAP Symposium on VLSI Technology and Circuits. That work demonstrated, for the first time, scaled nFETs (MoS₂ channel) and pFETs (WS₂ or WSe₂ channel) with a 50 nm contacted poly pitch on a 300 mm wafer, with 94% of transistors operational. The two efforts address complementary problems: the imec-ASML-TSMC work tackles integration pitch and CMOS compatibility; the NYCU-TSMC paper targets the gate-dielectric interface quality that determines whether individual devices actually perform.

The fabrication steps in the NYCU-TSMC approach - epitaxial aluminum deposition and controlled oxidation - do not require fundamentally new equipment categories, which matters for any eventual transition from research to manufacturing.

The immediate question is whether the 0.42 nm buffer holds up under the contact-resistance and parasitic-capacitance constraints that imec identified as the binding limits for 2D GAA devices at the A2 node. That intersection - interface quality meeting pitch scaling - is where the next set of results will be worth watching.