MIT-led team uses ultrafast X-ray diffraction to map heat flow in GaN-on-silicon thin films
Researchers from MIT, SLAC, Stanford, and Argonne published a non-contact X-ray method that maps in-plane thermal conductivity and interfacial conductance in GaN thin films, revealing a fourfold conductivity drop near a single wrinkle defect.

A team from MIT, SLAC National Accelerator Laboratory, Stanford University, and Argonne National Laboratory published a non-contact technique on 6 August 2026 that uses ultrafast X-ray diffraction to map thermal transport inside GaN thin films on silicon - resolving both in-plane thermal conductivity and thermal boundary conductance simultaneously[1]. The most striking result: a single micron-scale wrinkle defect caused a fourfold reduction in local thermal conductivity and a 25% drop in interfacial conductance at that spot[1].
Why existing thermometry falls short
Conventional techniques - time-domain thermoreflectance, the 3ω method, Raman thermometry, and scanning thermal probes - share a common weakness in multilayer stacks[1]. They are constrained by surface sensitivity, require metal transducers, or return only depth-averaged values that cannot isolate individual buried layers. Optical methods in particular lack the penetration depth to resolve interfaces inside a device, and infrared cameras lack the frame rate needed for nanoscale dynamics[1].
The new approach sidesteps these limits by exploiting the deep penetration and sub-picometer lattice sensitivity of hard X-rays. A laser pulse heats the sample; a synchronized ultrafast X-ray beam - sourced from the Linac Coherent Light Source at SLAC and the Advanced Photon Source at Argonne - probes the resulting lattice strain as heat spreads laterally[1]. Tracking that strain field over time lets the team reconstruct the full spatiotemporal heat-flow map without touching the device.
What the GaN measurement revealed
The model system was a ~100 nm GaN film transferred onto silicon, a stack of direct interest for high-electron-mobility transistors and flexible electronics[1]. Key findings from the measurement:
- Heat dissipation was asymmetric across the wrinkle: it moved more easily in one lateral direction than the other[1].
- Local thermal conductivity near the wrinkle fell to roughly one-quarter of the bulk value[1].
- Interfacial conductance dropped 25% at the same location, compounding the thermal bottleneck[1].
The team modeled the dynamics by solving the three-dimensional heat conduction equation with a spatially dependent conductivity tensor, confirming that the diffusive regime applies at the ~100 nm film thickness used[1].
Design implications
MIT associate professor Jeehwan Kim framed the practical value directly: "This will enable better thermal design of electronic systems. Even with the same type of materials, the geometry and how the materials are laid out is quite complicated, so it will show us how those differences impact thermal flow by providing direct experimental measurements."[1] The approach could help chip designers locate hidden thermal bottlenecks introduced during film transfer - a step that routinely generates wrinkles and other microscale defects - before committing to a layout.
The paper, authored by Thanh Nguyen, Chuliang Fu, Mouyang Cheng, and colleagues, appeared in Nature Communications (DOI: 10.1038/s41467-026-75414-w)[1].
The immediate question is whether the technique can be adapted to thinner films and more complex stacks - AlGaN/GaN HEMTs, for instance - and whether synchrotron access requirements can be relaxed through advances in laboratory-scale X-ray sources. If so, spatiotemporal thermal mapping could move from a research diagnostic into a routine step in power-device qualification.
Written by Electronics Insider's automated desk from the sources above and published automatically. How we work.
Related
Design & EDASignaloid founder Phillip Stanley-Marbell steps down from Cambridge chair to run probabilistic computing startup full-time
SemiWiki's CEO interview with Phillip Stanley-Marbell traces his path from Bell Labs and Apple to founding Signaloid, a Cambridge spinout whose C0-ASIC targets 1000× performance-per-watt gains.
22 Aug 2026TSMC's COUPE co-packaged optics platform enters production in the second half of 2026
TSMC's Compact Universal Photonic Engine moves from qualification to volume production in H2 2026, promising 2x power efficiency and 10x lower latency over pluggable optics.
22 Aug 2026
SemiconductorsSemiconductor Engineering frames energy efficiency as the defining constraint for AI computing through 2030
Data center electricity is set to nearly double to 945 TWh by 2030, making energy efficiency the central strategic challenge - and opportunity - for every company deploying AI at scale.
22 Aug 2026