Cadence's Amol Borkar explains why AI voice at the edge demands a rethink of SoC architecture, not just faster processors

Semiconductor Engineering published an interview with Amol Borkar, group director of product management and marketing for Tensilica DSPs at Cadence, on 9 September 2026, examining how increasingly capable natural language processing is changing the way audio systems are designed, integrated, and perceived at the edge^[1]. The piece is less a product announcement than a design-philosophy argument: the shift from menu-navigation voice to genuinely conversational human-machine interfaces requires rethinking what an audio SoC is asked to do, not simply clocking it faster^[1].

From menu navigation to conversational AI

Voice-based navigation has existed in consumer and automotive devices for roughly two decades, but the interaction model was narrow - users learned to speak in system-defined phrases and tolerate rigid, numbered responses^[1]. The addition of AI has broken that constraint. Modern NLP pipelines running on edge SoCs can handle keyword spotting (KWS), active noise cancellation (ANC), beamforming, and automatic speech recognition (ASR) as a continuous, integrated stack rather than sequential discrete steps.

The design consequence is significant. Edge voice SoCs must execute inference tasks such as wake-word recognition and intent parsing in under 100 milliseconds while consuming only milliwatts of power - a combination that rules out cloud round-trips for the latency-sensitive portion of the pipeline. Borkar's argument, as reported by Semiconductor Engineering, is that this constraint makes the DSP the right architectural anchor: a programmable, power-efficient core that can run the full audio pre- and post-processing chain alongside compact language models, without the overhead of a separate dedicated accelerator^[1].

Why raw compute is the wrong metric

Power-constrained edge designs cannot simply raise operating frequency or add cores to meet NLP workload growth. Increasing clock speed raises dynamic power quadratically; adding cores multiplies area and static leakage. The practical ceiling for always-on voice processing in consumer and automotive SoCs is a sub-1 W power envelope, which forces architects toward workload-specific instruction sets and data-path widths rather than brute-force scaling.

Cadence's response with the sixth-generation Tensilica HiFi iQ DSP - announced in January 2026 and now in general availability - illustrates the approach: the architecture delivers 2x compute performance and 8x higher AI throughput versus the prior HiFi 5s generation, while cutting energy consumption by more than 25% for most workloads. The gains come from a wider execution unit built on the Xtensa LX8 platform and native support for FP8 and BF16 formats, which allow quantized small language models (SLMs) to run directly on the DSP without offloading to a separate NPU. When additional headroom is needed, the HiFi iQ can be paired with Cadence's Neo NPUs.

A July 2026 demonstration by MosChip and Cadence showed the practical result: a quantized SLM voice assistant running entirely on-device on a Tensilica Vision Q7 DSP inside an Axera AX650N platform, with no cloud connection. The full loop - spoken input to ASR, SLM inference, text-to-speech output - ran locally, keeping data on the device and eliminating round-trip latency.

What the design community should watch

The Semiconductor Engineering interview signals that the competitive pressure in voice-enabled SoC design is moving from raw TOPS numbers toward energy-per-inference and programmability. The next inflection point Borkar points to is cache-coherent multicore DSP configurations - planned for a future HiFi iQ revision - which would let voice and audio workloads share memory with application processors without the latency penalty of explicit data transfers. Whether that capability arrives in time for the next automotive infotainment design cycle, where road-noise cancellation and in-cabin NLP are converging on the same SoC, will be worth tracking.