FlowAccel's Joel Jorgensen argues chip teams must design their workflows before AI can help them hit tape-out

Joel Jorgensen, founder of FlowAccel and a 25-year Intel veteran, published the first instalment of a new series on 14 October 2026 arguing that semiconductor engineering teams are adopting AI point-by-point - mostly in verification - without first designing the cross-team workflows that would let those tools compound into schedule gains^[1]. The central claim: if you haven't written the score, the orchestra can't play together.

Verification is where AI landed, but integration is still thin

The 2026 Siemens EDA and Wilson Research Group Functional Verification Study found that 82.8% of teams are using AI in verification beyond evaluation or pilot projects, yet only 9% describe AI as broadly integrated across the verification flow. The leading applications are debug and root-cause analysis, testbench and test generation, and coverage modeling and analysis - all point tasks, not end-to-end flows.

That selective adoption matters because verification is already the schedule's biggest consumer. The 2026 Siemens EDA and Wilson Research Group study found that verification consumes roughly half of project time across IC and FPGA programs, and most projects are behind schedule. Jorgensen's argument is that AI applied to individual verification tasks without a designed workflow around it can mask the real bottleneck rather than remove it^[1].

The first-silicon picture reinforces the urgency. Among IC/ASIC respondents in the 2026 Wilson Research Group study, only 5% reported first-silicon success, down from 14.4% in 2024. That collapse happened while AI tool adoption was rising - which suggests tool adoption alone is not the lever.

The handoff problem nobody is designing around

Jorgensen draws a pointed contrast: chip teams meticulously design every signal path on a chip - timing it, margining it, testing it - but almost nobody applies the same discipline to the path a decision takes between two teams^[1].

The RTL-to-verification handoff, the hardware-to-firmware boundary, the design-to-validation transition: Jorgensen cites Microsoft's 2026 Work Trend Index finding that even among the most advanced AI users, only about a quarter have their handoffs and quality standards documented and repeatable across the organization. That figure comes from a study of 20,000 knowledge workers across 10 countries, and it maps directly onto what Jorgensen observes in silicon development organisations^[1].

The Microsoft data adds texture. Among so-called Frontier Professionals - the top 16% of AI users - those with documented, repeatable handoffs at the team, function, and organisation level are significantly more likely to report that AI is producing work they couldn't have done a year ago. The implication for chip teams: the ceiling on AI's schedule impact is set not by the tools but by the workflow structure around them.

What "writing the score" means in practice

Jorgensen uses the orchestral score as a working metaphor: the written music that lays out every section's part on the same page so they play together^[1]. In a chip programme, that score is the designed workflow - owned at every level, the way you'd design a chip: blocks, subsystems, the SoC^[1].

The practical implication is a sequencing question. Before asking which AI tool to deploy in verification, a director needs to know:

• Which handoffs between teams are undocumented or inconsistent
• Where quality standards for AI-assisted outputs have not been agreed
• Which integration points between RTL, verification, firmware, and validation are load-bearing for the schedule

This is consistent with what TSMC and its EDA partners have been building toward. TSMC has been working with partners to create AI-driven design flows supported by AI Design Kits, with the goal of using AI to improve chip design flows and methodologies. Cadence has described a shift from tool-by-tool workflows to goal-driven, agentic execution. Siemens has introduced self-verifying agentic workflows that validate decisions against physics-based EDA engines. But all of those capabilities assume a team that knows where its workflow boundaries are - which is precisely what Jorgensen says most teams have not yet mapped.

What to watch

Jorgensen has flagged this as Part 1 of a series, with subsequent instalments expected to address how teams can audit and redesign their workflows once the score is written^[1]. The timing is deliberate: TSMC's AI Design Kit ecosystem is maturing, agentic EDA tools from Cadence, Siemens, and Synopsys are moving from demo to certified production flows, and the 2026 Wilson data has given directors a hard number - 5% first-silicon success - that is difficult to ignore in a roadmap conversation. Whether the industry responds by redesigning workflows or by layering more tools onto broken ones is the question the series is set up to answer.