ETH Zürich and NYU find JEDEC test loops underestimate HBM2 power by up to 35.4%

Researchers at ETH Zürich and New York University submitted a paper on 9 October 2026 showing that real-world HBM2 access patterns can draw up to 35.4% more power than the highest-power-consuming JEDEC-specified current measurement loop^[1], a gap large enough to trigger thermal throttling or shutdown in AI and HPC systems that rely solely on vendor test specifications for thermal budgeting.

What the team measured and how

The paper - "Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips," arXiv:2610.14244 - describes the first comprehensive experimental characterization of power consumed by real HBM2 DRAM chips^[1]. The team built a custom FPGA-based testing platform on top of the DRAM Bender infrastructure, running it across 36 HBM2 chips mounted on 18 AMD Alveo U55C FPGA boards.

The characterization produced 13 new findings and 6 key takeaway messages^[1]. Three stand out:

• A read operation draws 3.1× more current than a refresh operation, making it the highest-current operation tested.
• Read current varies across bank groups by 8.1% and across banks by 5.3%, meaning structural position inside the chip matters for power draw.
• Toggling all HBM2-internal bank group bus signals during a data transfer burst causes 29.4% higher power consumption than keeping those signals constant^[1].

Using those insights, the team engineered a deliberate access pattern that produced 23.6% higher power consumption on average - and 35.4% higher at peak - across all 36 tested chips compared with the highest-power JEDEC current loop^[1].

Why the JEDEC gap matters for system designers

The implication is direct: an HBM2-based system sized to the JEDEC or vendor IDD test loops may be under-provisioned for real AI and HPC workloads. The paper states that relying solely on those loops "could cause errors or system failures, thermal throttling, and thermal shutdowns in real-world high-power, high-performance computing or AI/ML workloads."^[1]

This is not a theoretical concern. Thermal throttling in HBM is already documented to reduce bandwidth by roughly 27% and increase read latency by 70% under sustained high-temperature operation. As AI accelerators push HBM stacks harder - the NVIDIA H200 carries 141 GB of HBM3E across six stacks, and the B200 carries 192 GB - the margin for error in power budgeting narrows with each generation.

A new power model to replace the gap

Beyond characterization, the team developed a new HBM power model validated against the same 36 chips across diverse workloads, including a real LLM decode workload. The model achieves 7.6-8.1% mean absolute percentage error, compared with 20-42% for state-of-the-art HBM power models. The team also validated it against HBM3E GPU memory power consumption, extending its relevance beyond the HBM2 generation tested.

The model is intended for integration into open-source architectural simulation infrastructures, giving chip architects a more accurate tool for power-aware memory subsystem design.

The paper's findings arrive as the industry is actively trying to squeeze more performance from tighter power envelopes. NVIDIA's NVHBM interface, announced for next-generation accelerators, targets 15% lower HBM power versus standard HBM4e - a saving that only compounds in value if the baseline power figure is accurately known in the first place. Whether simulation tools and system validation flows will be updated to reflect the ETH Zürich and NYU characterization data is the question to watch.