Eric Hong outlines Mixel's mixed-signal IP strategy after Silvaco acquisition

In an interview published on 13 October 2026 on SemiWiki, Eric Hong - Vice President of Engineering at Mixel, a Silvaco company - laid out how the mixed-signal IP specialist is positioning its PHY and SerDes portfolio after being absorbed into Silvaco in August 2025^[1]. The conversation is the clearest public statement yet on where Mixel's engineering priorities sit inside its new parent.

Background: Mixel inside Silvaco

Silvaco completed its acquisition of Mixel Group, Inc. on 4 August 2025, folding the San Jose-based IP provider into its Semiconductor IP Business Unit. The deal was structured as a combination of cash and stock^[1]. Silvaco's stated rationale was to expand its connectivity IP reach into mobile, automotive, VR/AR, IoT, and robotics - markets where Mixel had established silicon-proven credentials across more than 25 years of operation.

Hong joined Mixel after engineering leadership stints at Nvidia, eSilicon, Samsung Electro-Mechanics, and Intel^[1]. He holds eight patents and earned a B.S. in Electrical Engineering from UC Berkeley and an M.S. in Electrical Engineering from Stanford University^[1]. He cited Mixel's culture of customer focus and its close relationships with leading foundries and SoC developers as the factors that drew him to the company^[1].

What the IP portfolio covers

Mixel's current offering spans three MIPI PHY families and a set of multi-standard SerDes combo IPs:

• MIPI D-PHY v3.5 - up to 6.5 Gbps per lane, supporting MIPI CSI-2 and DSI/DSI-2
• MIPI C-PHY v2.1 - up to 8.0 Gsps per trio (18.24 Gbps equivalent), supporting CSI-2 and DSI/DSI-2
• MIPI M-PHY v4.1 - up to 11.6 Gbps, supporting UniPro and JEDEC UFS
• C-PHY/D-PHY combo and LVDS/D-PHY combo multi-standard SerDes
• ASA Motion Link SerDes - automotive long-reach, asymmetric connectivity

The IP is silicon-proven across nine foundries and twelve process nodes, from 180 nm down to 5 nm. A proprietary MIPI D-PHY RX+ topology - patented and in production since 2015 - allows full-speed production testing without a full Universal configuration, cutting die area by 35% and leakage power by 50% versus a standard D-PHY Universal implementation.

The TSMC N2P milestone

The most recent product milestone predating the interview was the 19 May 2026 availability of the Mixel MIPI C-PHY/D-PHY Combo Universal IP on TSMC's N2P process. The combo IP is claimed to be the industry's first to support MIPI D-PHY v3.6 with embedded clock mode (ECM) - a feature first introduced in the D-PHY v3.5 specification. In ECM, the clock is embedded in the data stream rather than forwarded on a dedicated lane, achieving similar throughput with roughly 25% fewer wires compared with a standard forwarded-clock combo. The IP targets AR glasses, wearables, and other form factors where wire count, EMI, and heat dissipation are tightly constrained.

What to watch

Hong's interview signals that Mixel intends to keep pushing to leading-edge nodes under Silvaco's ownership, with automotive connectivity - including ISO 26262-compliant IPs - a stated growth priority. The next indicator to watch is whether Mixel extends its N2P combo IP to additional foundry partners, and whether the ASA Motion Link SerDes reaches silicon-proven status on an advanced node in the near term.