Sandia and Luxembourg researchers map the exact leakage route in gate-all-around transistors

Researchers at Sandia National Laboratories and the Luxembourg Institute of Science and Technology (LIST) posted an arXiv preprint on 9 October 2026 that, for the first time, spatially resolves the leakage pathway inside a gate-all-around field-effect transistor (GAAFET) - the transistor architecture now entering high-volume production at the 2 nm node^[1].

The problem: leakage that defies the textbook

GAAFETs are the designated successors to FinFETs at advanced semiconductor nodes below 3 nm, adopted by Samsung at 3 nm in 2022 and by TSMC and Intel at 2 nm through 2025-2026. Their defining advantage is improved electrostatic control: the gate wraps entirely around the channel on all four sides, tightening the grip on current flow.

That advantage comes with an unexpected liability. Recent measurements show that drain current in GAAFETs deviates strongly from thermionic behavior at negative gate voltages, rising as the gate voltage becomes more negative^[1] - the opposite of what ideal transistor physics predicts. The team's earlier work, published in Journal of Applied Physics in June 2026, identified the mechanism as direct gate-drain tunneling through the high-k dielectric, amplified by a newly named effect called drain-induced dielectric barrier lowering (DIDBL)^[1]. That paper established the terminal-level picture; what remained unknown was exactly where inside the device the leakage current flows.

What the new simulation reveals

The October 2026 paper closes that gap. The authors - Denis Mamaluy, Juan P. Mendez, Coleman Cariker, Michael Titze, and Alex A. Belianinov - applied a charge-self-consistent Non-Equilibrium Green Function (NEGF) framework built on the Contact Block Reduction (CBR) method^[1].

The key distinction from conventional NEGF tools is how the gate is treated. Most implementations handle the gate purely electrostatically, through a Poisson potential, and cannot model it as a source of injected carriers. The CBR-based multi-terminal framework treats the source, drain, and gate as current-carrying quantum-mechanical contacts, enabling direct resolution of gate-related leakage paths^[1].

The spatially resolved current density produced by the simulation shows three things clearly:

• Carriers injected from the gate tunnel through the high-k dielectric preferentially on the drain side of the gate stack, not uniformly across it^[1].
• The drain bias lowers the effective dielectric tunnel barrier between gate and drain - the DIDBL mechanism - concentrating leakage at that corner of the device^[1].
• The gate-drain leakage mechanism identified computationally has since been independently confirmed by experiment^[1].

The device modeled uses a 2 nm HfO₂ high-k dielectric with a dielectric constant of ε = 20 and an electron barrier height of 1.6 eV, parameters representative of current production stacks.

Why it matters for scaling

The prior Sandia/LIST work established that solving the GAAFET leakage problem requires addressing at least two issues to push physical gate lengths below 10 nm: reducing the gate leakage current induced by drain bias, and managing the related electrostatic effects. Knowing the spatial pathway - not just the terminal currents - gives process engineers a concrete target. Dielectric thickness, material choice, and gate-to-drain geometry can now be optimized against a mapped leakage route rather than an inferred one.

The paper is available as arXiv preprint 2610.14298 under a Creative Commons license. As foundries ramp 2 nm GAA production and begin development of sub-2 nm nodes, whether the DIDBL mechanism worsens with further gate-length scaling - and whether thinner or alternative high-k materials can suppress it - will be the next question to watch.