NVIDIA details Vera CPU's Olympus core architecture at Hot Chips 2026, claiming 1.8x agentic AI speedup

NVIDIA presented the internal microarchitecture of its Vera CPU at Hot Chips 2026 on 24 August 2026, giving the most detailed public disclosure of the chip to date^[1]. The processor, built around 88 custom Olympus cores and a SOCAMM2 LPDDR5X memory subsystem delivering up to 1.2 TB/s of bandwidth, is positioned as the host CPU for the Vera Rubin NVL72 rack-scale platform and NVIDIA's successor to the Grace-based designs that anchored Grace Hopper and Grace Blackwell. All performance figures cited below are NVIDIA claims; several results were based on preproduction or unofficial testing^[1].

Why agentic workloads demand a different CPU

The design rationale starts with how AI agents actually run. When a language model is orchestrating tools, executing code in a sandbox, parsing API responses, or deciding what to do next, a large share of the compute budget falls on the CPU rather than the GPU. That sequential, branch-heavy execution path is latency-sensitive in a way that high-core-count, lower-IPC server CPUs were not built to handle. NVIDIA's argument is that server economics have pushed x86 designs toward maximising rentable core counts at the expense of per-thread speed - the wrong trade-off for agentic workloads where the critical path is serial^[1].

Olympus core: wide front end, spatial multithreading

The Olympus core is an Armv9.2-compatible, out-of-order design with a 10-wide instruction decode stage and a neural branch predictor. NVIDIA calls its two-thread-per-core implementation Spatial Multithreading: rather than time-slicing all core resources between threads as conventional SMT does, it statically partitions execution resources between the two threads, allowing one to run a latency-sensitive agent task while the other handles system or management work with less interference. Across 88 cores, Vera exposes 176 threads in total.

The on-die fabric - NVIDIA's Scalable Coherency Fabric - provides 3.4 TB/s of core-to-core bandwidth and a 164 MB unified L3 cache. The SOCAMM2 memory subsystem runs at up to 9,600 MT/s, with eight modules per board supporting between 256 GB and 1.5 TB of capacity. Connectivity options include:

• NVLink-C2C at 1.8 TB/s for coherent GPU attachment
• PCIe Gen 6.4 with 88 lanes per CPU
• CXL 3.1 for memory expansion
• Arm Confidential Computing Architecture (CCA) for secure VM isolation

The monolithic compute die - rather than a chiplet layout - is a deliberate choice to reduce latency across the fabric.

Performance claims and competitive context

NVIDIA claims Vera completes agentic workloads up to 1.8x faster than leading x86 CPUs, and compiles the Linux kernel 14-22% faster than AMD's 96-core EPYC 9655P. On a per-core basis, internal July 2026 testing puts Vera at up to 1.5x the agentic throughput of AMD's Venice CPUs, attributed to the monolithic die, wide front end, and high-bandwidth memory subsystem. AMD responded at the same conference with a claim that its upcoming 256-core Zen 6 Venice delivers 3.3x higher rack-level performance than Vera - a figure that measures a different configuration and should be treated as a vendor claim until independent testing is available.

The competitive pressure is real: Google Axion, Amazon Graviton, and Microsoft Cobalt are all in production at hyperscalers, and Vera's detailed public disclosure at Hot Chips signals that NVIDIA is working to keep CPU economics inside its own platform before customers lock in alternatives. The next test will be independent benchmarks on production Vera Rubin NVL72 systems, and whether the agentic-workload gains hold when measured against Venice and Intel's Diamond Rapids on comparable rack configurations.