Washington State and UW-Madison propose an LSTM-driven framework that cuts voltage droop EDP by 76x in 2.5D PIM chiplet systems

Researchers from Washington State University and the University of Wisconsin-Madison published a paper in August 2026 describing ReVolt, a runtime framework that prevents voltage droop violations in processing-in-memory (PIM) 2.5D multi-chiplet platforms^[1]. The headline result: an average 76x reduction in energy-delay product (EDP) compared to existing fixed and dynamic operation-unit baselines, with no loss in ML model inference accuracy^[1].

Why voltage droop is a first-order problem in PIM chiplet design

PIM-based 2.5D multi-chiplet platforms are increasingly used as accelerators for machine learning workloads, but their power delivery network (PDN) creates a structural hazard^[1]. As each chiplet's compute activity fluctuates, its current draw changes - and because the PDN has finite impedance, those current transients translate directly into spatially and temporally varying voltage droop across the interposer^[1].

The consequences compound quickly:

• Voltage violations force guard-banding or clock throttling, degrading throughput.
• Droop events that cross timing margins corrupt computation, reducing ML inference accuracy.
• Existing mitigations - fixed or dynamically sized operation units (OUs) - react after the fact, leaving the system exposed during the droop transient^[1].

The 2.5D geometry makes the problem harder than in a monolithic die. Each chiplet sits at a different electrical distance from the package voltage regulators, so droop magnitude and timing differ per chiplet, and a single global policy cannot optimally serve all of them simultaneously.

How ReVolt works

ReVolt treats OU size as a runtime control knob and adjusts it proactively rather than reactively^[1]. The framework has two coupled components:

1. LSTM-based PDN surrogate. A long short-term memory network, trained offline on PDN simulation data, predicts per-chiplet supply voltage trajectories at runtime. Because LSTMs capture temporal dependencies in sequential signals, the surrogate can anticipate a droop event before it reaches a violation threshold^[1].
2. OU-size controller. When the surrogate forecasts an impending droop, ReVolt reduces the active OU count on the affected chiplet, cutting its instantaneous current demand. When voltage headroom is adequate, it restores full OU utilization to recover throughput^[1].

By treating OU size as a control knob, ReVolt regulates chiplet-level current demand while maintaining computational accuracy^[1]. The key insight is that OU granularity maps cleanly onto current draw: fewer active OUs means a proportionally smaller current spike, and the LSTM surrogate gives enough lead time to act before the PDN voltage collapses.

Experimental results

The paper reports that ReVolt prevents all voltage droop violations across the tested workloads while achieving the 76x EDP improvement over baselines^[1]. Inference accuracy of the ML models under test is preserved - the OU throttling is fine-grained enough that it does not introduce meaningful approximation error^[1].

The full paper, "ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures," is available at arXiv:2608.08496. Authors are Vibhanshu Sharma, Alish Kanani, Miao Sun, Janardhan Rao Doppa, Umit Y. Ogras, and Partha Pratim Pande^[1].

The immediate question for designers is whether the LSTM surrogate generalises across different chiplet counts, interposer geometries, and PDN topologies beyond those tested. The team's prior work on multi-chiplet thermal modelling suggests the same group is building toward a broader co-design methodology for 2.5D systems - PDN-aware voltage control is a natural complement to that effort, and follow-on silicon validation would be the next credibility milestone to watch for.