Rise Design Automation launches IPCreate and IPTransform platforms at DAC 2026, claiming one million gates per engineer per week

Rise Design Automation used its DAC 2026 booth appearance to unveil two new platforms - IPCreate and IPTransform - and a new AI-powered flow that the company claims lets a single engineer produce roughly one million gates in a week from a written specification, a throughput it says is impossible with conventional hand-written RTL^[1].

What the two new platforms do

The tools address opposite ends of the design abstraction problem^[1]:

• IPCreate Platform takes a specification - or even a MathWorks model - as input, generates C++, SystemC, or SystemVerilog models, and after synthesis produces technology-optimized RTL^[1].
• IPTransform Platform runs in the reverse direction: it starts from existing RTL plus a testbench, uses AI reasoning on the elaborated design to check claims against the specification, and raises the design to a high-level HLS model^[1].

Both tools were written primarily by human engineers, with some LLM-generated code produced using tools such as Claude Code^[1].

Why HLS sits in the middle

The new AI-powered flow routes through a High Level Synthesis (HLS) intermediate model rather than going directly from specification to RTL^[1]. The rationale is simulation throughput: Rise claims its high-level models simulate 30× faster than equivalent RTL models^[1]. That speed advantage matters because design teams are routinely expected to deliver new products in nine months to a year, and specifications frequently change late in a project^[1].

Emulation can also accelerate simulation, but Rise notes it is expensive^[1]. The HLS route is positioned as a lower-cost path to the same capacity benefit. The company says its HLS flow has also overcome earlier quality-of-results (QoR) and timing challenges that historically made HLS outputs difficult to hand off to downstream synthesis^[1].

What the flow accepts and produces

Rise supports several entry points for the flow^[1]:

• MathWorks models
• C++
• SystemC
• SystemVerilog

IPTransform's output - a raised HLS model and regenerated specification - can be simulated directly, giving teams a fast, high-level representation of legacy RTL that can serve as a new single source of truth^[1]. The company argues that moving the source-of-truth up the abstraction stack enables larger system-level models for AI-era designs, reduces dependence on expensive emulators, and creates more architectural starting points to explore^[1].

Rise also cautions that using a general-purpose LLM such as Claude directly to go from specification to a high-level model carries risk: the model may generate code that cannot be synthesized, or may introduce hallucinations^[1]. The IPCreate flow is presented as a guardrailed alternative that keeps outputs synthesizable and verifiable.

Whether the one-million-gates-per-week claim holds across representative industrial designs - and how IPCreate's QoR compares with hand-coded RTL at advanced nodes - will be the questions to watch as early adopters put both platforms through production workloads.